RISC-V: From Development to Production

An evening dedicated to closing the gap between RISC-V development and RISC-V production.

Date
Thursday, 5 November 2026
Time
From 18:30
Location
Granada, Spain
Access
By invitation

RISC-V is at a turning point. What began as an open, experimental architecture has become production infrastructure: cores are shipping at scale, and the conversation across the ecosystem has shifted from whether the architecture works to how it gets deployed, qualified, and supported once it’s in the field. That shift changes what actually matters next.

The challenge ahead is no longer the architecture itself. It is the layer that sits between a validated core and a shippable product: the tooling, the safety qualification pathways, and the talent pipeline that turn research into something an industry can build on with confidence. Whoever helps close that layer determines how quickly RISC-V research becomes deployable product, and who ultimately captures the value it creates.

This makes it a collective challenge rather than one any single institution can solve alone. The infrastructure a production-ready RISC-V ecosystem needs has to be built across boundaries: between the university research groups producing the work, the industry teams responsible for shipping it, the partners building the tooling around it, and the talent who will carry it forward. Progress depends on that collaboration happening by design, not by accident.

This event is built around exactly that collaboration. Keynotes from university research groups, industry experts, and research centers will surface where the real gaps are. A panel discussion will bring researchers and industry into the conversation on commercialization, tooling gaps, talent, and funding. The evening will close with a reception built for the follow-up conversations that actually move projects forward.

Agenda

Three keynotes, one panel and an evening to keep the conversation going.

18:45

Welcome and opening

19:00

Keynote

Challenges and Opportunities for Benchmarking RISC-V Automotive MPSoCs

Jaume Abella
Director, High Performance Embedded Systems Laboratory · BSC

19:15

Keynote

RISC-V as an enabler, yet so much more

Thomas Roecker
Architect · Infineon

19:30

Keynote

Freedom with Guardrails: Evolving an Open ISA Without Breaking It

Prof. Dr. Stefan Wallentovitz
Professor · Munich University of Applied Sciences

19:45

Panel discussion

Bridging RISC-V Research and Commercial Reality

Moderator
Quintauris

Panelists
Kenneth Rovers
Principal Member of Technical Staff, Compute System Architecture (CSA) · imec

Pedro Marcuello
Fellow Engineer · Semidynamics

Prof. Dr. Stefan Wallentovitz
Professor · Munich University of Applied Sciences

About the panel

Most RISC-V research is strong on its own terms. Much of it never reaches a product. The reason is rarely the quality of the idea. It is usually the distance between how research is funded, measured and staffed and what production actually demands: tooling that holds up, long-term support, certification and people who can carry the work forward.

No single institution can close that distance alone. It is a shared problem across the ecosystem. That is why the panel puts one voice from industry R&D, one from a university and one from a research center at the same table.

You will leave with:

  • A clear picture of the few blockers that most often stop research from reaching production.
  • Concrete ways academia, research centers and industry can work together differently, starting with the people in the room.
  • A reason to keep the conversation going at the reception.

This is not a showcase of results. Expect an honest account of where things get stuck, drawn from the panelists’ own experience.

20:30

Reception

Networking reception

Continue the discussion with speakers, panelists and peers from academia, research and industry.

Attendance is by invitation

Seats are limited. Request your invitation and we will get back to you.

Request an invitation

Speakers